Epson Arm S1C31 Series Technical Manual page 396

APPENDIX A LIST OF PERIPHERAL CIRCUIT CONTROL REGISTERS
Address Register name
0x0020 UART3_2BR
0624 (UART3 Ch.2 Baud-
Rate Register)
0x0020 UART3_2CTL
0626
(UART3 Ch.2 Control
Register)
0x0020 UART3_2TXD
0628 (UART3 Ch.2 Trans-
mit Data Register)
0x0020 UART3_2RXD
062a
(UART3 Ch.2 Receive
Data Register)
0x0020 UART3_2INTF
062c (UART3 Ch.2 Status
and Interrupt Flag
Register)
0x0020 UART3_2INTE
062e (UART3 Ch.2
Interrupt Enable
Register)
0x0020 UART3_2
0630 TBEDMAEN
(UART3 Ch.2
Transmit Buffer
Empty DMA Request
Enable Register)
0x0020 UART3_2
0632 RB1FDMAEN
(UART3 Ch.2 Receive
Buffer One Byte Full
DMA Request Enable
Register)
0x0020 UART3_2CAWF
0634
(UART3 Ch.2 Carrier
Waveform Register)
0x0020 0660–0x0020 066c
Address Register name
0x0020 T16_6CLK
0660 (T16 Ch.6 Clock
Control Register)
0x0020 T16_6MOD
0662
(T16 Ch.6 Mode
Register)
AP-A-34
Bit Bit name
15–12 –
11–8 FMD[3:0]
7–0 BRT[7:0]
15–8 –
7–2 –
1 SFTRST
0 MODEN
15–8 –
7–0 TXD[7:0]
15–8 –
7–0 RXD[7:0]
15–10 –
9 RBSY
8 TBSY
7 –
6 TENDIF
5 FEIF
4 PEIF
3 OEIF
2 RB2FIF
1 RB1FIF
0 TBEIF
15–8 –
7 –
6 TENDIE
5 FEIE
4 PEIE
3 OEIE
2 RB2FIE
1 RB1FIE
0 TBEIE
15–8 –
7–4 –
3–0 TBEDMAEN[3:0]
15–8 –
7–4 –
3–0 RB1FDMAEN[3:0]
15–8 –
7–0 CRPER[7:0]
Bit Bit name
15–9 –
8 DBRUN
7–4 CLKDIV[3:0]
3–2 –
1–0 CLKSRC[1:0]
15–8 –
7–1 –
0 TRMD
Seiko Epson Corporation
Initial Reset R/W
0x0 – R
0x0 H0 R/W
0x00 H0 R/W
0x00 – R
0x00 – R
0 H0 R/W
0 H0 R/W
0x00 – R
0x00 H0 R/W
0x00 – R
0x00 H0 R
0x00 – R
0 H0/S0 R
0 H0/S0 R
0 – R
0 H0/S0 R/W
0 H0/S0 R/W
0 H0/S0 R/W
0 H0/S0 R/W
0 H0/S0 R
0 H0/S0 R
1 H0/S0 R
0x00 – R
0 – R
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0x00 – R
0x0 – R
0x0 H0 R/W
0x00 – R
0x0 – R
0x0 H0 R/W
0x00 – R
0x00 H0 R/W
16-bit Timer (T16) Ch.6
Initial Reset R/W
0x00 – R
0 H0 R/W
0x0 H0 R/W
0x0 – R
0x0 H0 R/W
0x00 – R
0x00 – R
0 H0 R/W
S1C31D41 TECHNICAL MANUAL
Remarks
–
–
–
–
–
Cleared by writing 1.
Cleared by writing 1 or read-
ing the UART3_2RXD register.
Cleared by writing 1.
Cleared by reading the
UART3_2RXD register.
Cleared by writing to the
UART3_2TXD register.
–
–
–
–
Remarks
–
–
(Rev. 1.1)