Epson Arm S1C31 Series Technical Manual page 168

(
Assert the slave select signal output from
Read the SPIA_nINTF.TBEIF bit
(
Negate the slave select signal output from
Data transmission using DMA
By setting the SPIA_nTBEDMAEN.TBEDMAENx bit to 1 (DMA transfer request enabled), a DMA transfer
request is sent to the DMA controller and transmit data is transferred from the specified memory to the SPIA_
nTXD register via DMA Ch.x when the SPIA_nINTF.TBEIF bit is set to 1 (transmit buffer empty).
This automates the procedure from Step 2 to Step 5 described above.
The transfer source/destination and control data must be set for the DMA controller and the relevant DMA
channel must be enabled to start a DMA transfer in advance so that transmit data will be transferred to the
SPIA_nTXD register. For more information on DMA, refer to the "DMA Controller" chapter.
Table 14.5.2.1 DMA Data Structure Configuration Example (for 16-bit Data Transmission)
End pointer
Control data dst_inc
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
Data transmission
a general-purpose port
SPIA_nINTF.TBEIF = 1 ?
YES
Write transmit data to
the SPIA_nTXD register
Transmit data remained?
NO
a general-purpose port
End
Figure 14.5.2.2 Data Transmission Flowchart in Master Mode
Item
Transfer source Memory address in which the last transmit data is stored
Transfer destination SPIA_nTXD register address
0x3 (no increment)
dst_size 0x1 (haflword)
src_inc 0x1 (+2)
src_size 0x1 (halfword)
R_power 0x0 (arbitrated for every transfer)
n_minus_1 Number of transfer data
cycle_ctrl 0x1 (basic transfer)
Seiko Epson Corporation
14 SYNCHRONOUS SERIAL INTERFACE (SPIA)
)
NO
YES
Wait for an interrupt request
(SPIA_nINTF.TBEIF = 1)
)
Setting example
14-7