Epson Arm S1C31 Series Technical Manual page 9

13.9 Control Registers ........................................................................................................ 13-11
UART3 Ch.n Clock Control Register ................................................................................. 13-11
UART3 Ch.n Mode Register .............................................................................................. 13-11
UART3 Ch.n Baud-Rate Register ...................................................................................... 13-13
UART3 Ch.n Control Register ............................................................................................ 13-13
UART3 Ch.n Transmit Data Register ................................................................................. 13-14
UART3 Ch.n Receive Data Register .................................................................................. 13-14
UART3 Ch.n Status and Interrupt Flag Register ................................................................ 13-14
UART3 Ch.n Interrupt Enable Register .............................................................................. 13-15
UART3 Ch.n Transmit Buffer Empty DMA Request Enable Register ................................ 13-16
UART3 Ch.n Receive Buffer One Byte Full DMA Request Enable Register ...................... 13-16
UART3 Ch.n Carrier Waveform Register ........................................................................... 13-16
14 Synchronous Serial Interface (SPIA) ........................................................................14-1
14.1 Overview ...................................................................................................................... 14-1
14.2 Input/Output Pins and External Connections .............................................................. 14-2
14.2.1 List of Input/Output Pins ................................................................................ 14-2
14.2.2 External Connections .................................................................................... 14-2
14.2.3 Pin Functions in Master Mode and Slave Mode ............................................ 14-3
14.2.4 Input Pin Pull-Up/Pull-Down Function .......................................................... 14-3
14.3 Clock Settings .............................................................................................................. 14-3
14.3.1 SPIA Operating Clock .................................................................................... 14-3
14.3.2 Clock Supply During Debugging ................................................................... 14-4
14.3.3 SPI Clock (SPICLKn) Phase and Polarity ...................................................... 14-4
14.4 Data Format ................................................................................................................. 14-5
14.5 Operations ................................................................................................................... 14-5
14.5.1 Initialization .................................................................................................... 14-5
14.5.2 Data Transmission in Master Mode ............................................................... 14-6
14.5.3 Data Reception in Master Mode .................................................................... 14-8
14.5.4 Terminating Data Transfer in Master Mode ................................................... 14-10
14.5.5 Data Transfer in Slave Mode ......................................................................... 14-10
14.5.6 Terminating Data Transfer in Slave Mode ..................................................... 14-11
14.6 Interrupts ..................................................................................................................... 14-12
14.7 DMA Transfer Requests .............................................................................................. 14-13
14.8 Control Registers ........................................................................................................ 14-13
SPIA Ch.n Mode Register .................................................................................................. 14-13
SPIA Ch.n Control Register ............................................................................................... 14-14
SPIA Ch.n Transmit Data Register ..................................................................................... 14-15
SPIA Ch.n Receive Data Register ...................................................................................... 14-15
SPIA Ch.n Interrupt Flag Register ..................................................................................... 14-15
SPIA Ch.n Interrupt Enable Register ................................................................................. 14-16
SPIA Ch.n Transmit Buffer Empty DMA Request Enable Register .................................... 14-16
SPIA Ch.n Receive Buffer Full DMA Request Enable Register ......................................... 14-16
15 Quad Synchronous Serial Interface (QSPI) .............................................................15-1
15.1 Overview ...................................................................................................................... 15-1
15.2 Input/Output Pins and External Connections .............................................................. 15-2
15.2.1 List of Input/Output Pins ................................................................................ 15-2
15.2.2 External Connections .................................................................................... 15-2
15.2.3 Pin Functions in Master Mode and Slave Mode ............................................ 15-6
15.2.4 Input Pin Pull-Up/Pull-Down Function .......................................................... 15-6
15.3 Clock Settings .............................................................................................................. 15-6
15.3.1 QSPI Operating Clock ................................................................................... 15-6
15.3.2 Clock Supply During Debugging ................................................................... 15-7
15.3.3 QSPI Clock (QSPICLKn) Phase and Polarity ................................................. 15-7
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
Seiko Epson Corporation
CONTENTS
vii