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When setting this mode, the timer function of the corresponding 16-bit timer channel may be used for an-
other purpose.
Use the 16-bit timer as a baud rate generator
By setting the QSPI_nMOD.NOCLKDIV bit to 0, the QSPI inputs the underflow signal generated by the
corresponding 16-bit timer channel and converts it to the QSPICLKn. The 16-bit timer must be run with an
appropriate reload data set. The QSPICLKn frequency (baud rate) and the 16-bit timer reload data are cal-
culated by the equations shown below.
f
= — — — — — — — — —
QSPICLK
2 × (RLD + 1)
Where
f
: QSPICLKn frequency [Hz] (= baud rate [bps])
QSPICLK
f
: QSPI operating clock frequency [Hz]
CLK_QSPI
RLD:
For controlling the 16-bit timer, refer to the "16-bit Timers" chapter.
Operating clock in slave mode
The QSPI set in slave mode operates with the clock supplied from the external SPI/QSPI master to the QSPI-
CLKn pin. The 16-bit timer channel (including the clock source selector and the divider) corresponding to the
QSPI channel is not used. Furthermore, the QSPI_nMOD.NOCLKDIV bit setting becomes ineffective.
The QSPI keeps operating using the clock supplied from the external SPI/QSPI master even if all the internal
clocks halt during SLEEP mode, so the QSPI can receive data and can generate receive buffer full interrupts.
15.3.2 Clock Supply During Debugging
In master mode, the operating clock supply during debugging should be controlled using the T16_mCLK.DBRUN
bit.
The CLK_T16_m supply to QSPI Ch.n is suspended when the CPU enters debug state if the T16_mCLK.DBRUN
bit = 0. After the CPU returns to normal operation, the CLK_T16_m supply resumes. Although QSPI Ch.n stops
operating when the CLK_T16_m supply is suspended, the output pins and registers retain the status before the de-
bug state was entered. If the T16_mCLK.DBRUN bit = 1, the CLK_T16_m supply is not suspended and QSPI Ch.n
will keep operating in a debug state.
The QSPI in slave mode operates with the external SPI/QSPI master clock input from the QSPICLKn pin regard-
less of whether the CPU is placed into debug state or normal operation state.
15.3.3 QSPI Clock (QSPICLK n ) Phase and Polarity
The QSPICLKn phase and polarity can be configured separately using the QSPI_nMOD.CPHA bit and the QSPI_
nMOD.CPOL bit, respectively. Figure 15.3.3.1 shows the clock waveform and data input/output timing in each set-
ting.
QSPI_nMOD register
CPOL bit
CPHA bit
1
1
QSPICLKn
1
0
QSPICLKn
0
1
QSPICLKn
0
0
QSPICLKn
x
x
(Master mode, output)
x
x
(Slave mode, output)
x
1
(Slave mode, output)
x
0
Figure 15.3.3.1 QSPI Clock Phase and Polarity (QSPI_nMOD.LSBFST bit = 0, QSPI_nMOD.CHLN[3:0] bits = 0x7)
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
f
CLK_QSPI
16-bit timer reload data value
Cycle No.
1
(Input)
QSDIOn
MSB
QSDIOn
MSB
QSDIOn
MSB
QSDIOn
MSB
Writing data to the QSPI_nTXD register
Seiko Epson Corporation
15 Quad Synchronous Serial Interface (QSPI)
f
CLK_QSPI
RLD = — — — — — — — — - 1
f
QSPICLK
2
3
4
(Eq. 15.1)
× 2
5
6
7
LSB
LSB
LSB
LSB
8
15-7
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