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REVISION HISTORY
Code No.
Page
414190501
16-7
16.4.3 Data Reception in Master Mode
Data receiving procedure
Added Step 1. (The old step numbers were carried down in order.)
1. When receiving one-byte data, write 1 to the I2CnCTL.TXNACK bit.
16-9
16.4.3 Data Reception in Master Mode
Data reception using DMA
Corrected the description.
This automates the data receiving procedure Steps 6, 8, and 10 described above.
22-17
22.4.3 External QSPI Flash Memory Access
Added a new section.
22-30
22.7 Control Registers
SDAC2 Control Register
Added a description on "Bit 0 SDACEN."
AP-A-37
Appendix A List of Peripheral Circuit Control Registers
QSPI_0MMACFG2 (QSPI Ch.0 Memory Mapped Access Configuration Register 2)
Modified the register table.
DUMDL[3:0], DUMLN[3:0]: Initial = 0x0 → 0x7
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