System Reset Controller (Src); Overview - Epson Arm S1C31 Series Technical Manual

Notes: • After the voltage mode has been switched, correct the RTC, as the RTC operating clock is
also stopped for the period set using the CLGOSC1.OSC1WT[1:0] bits.
• Always use the IC in mode0 when V
• When two voltage modes are used, set the V
into SLEEP or HALT mode.

2.2 System Reset Controller (SRC)

2.2.1 Overview

SRC is the system reset controller that resets the internal circuits according to the requests from the reset sources to
archive steady IC operations. The main features of SRC are outlined below.
• Embedded reset hold circuit maintains reset state to boot the system safely while the internal power supply is un-
stable after power on or the oscillation frequency is unstable after the clock source is initiated.
• Supports reset requests from multiple reset sources.
- #RESET pin
- POR and BOR
- Reset request from the CPU
- Watchdog timer reset
- Supply voltage detector reset
- Peripheral circuit software reset (supports some peripheral circuits only)
• The CPU registers and peripheral circuit control bits will be reset with an appropriate initialization condition ac-
cording to changes in status.
Figure 2.2.1.1 shows the SRC configuration.
#RESET
Reset request from CPU
Watchdog timer reset
Supply voltage detector reset
Software reset 0
Software reset n
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
is 3.6 V or higher.
DD
Clock generator
SRC
V
DD Reset request
signals
Noise filter
V
POR
SS
BOR
Figure 2.2.1.1 SRC Configuration
Seiko Epson Corporation
2 POWER SUPPLY, RESET, AND CLOCKS
regulator into mode1 before putting the IC
D1
Boot clock
IOSCCLK
Internal reset signals
(Reset group)
SYSRST_H0
Reset hold
circuit
SYSRST_H1
SYSRST_S0_0
Reset
decoder SYSRST_S0_n
To CPU and peripheral circuits
To CPU and peripheral circuits
To peripheral circuit 0
To peripheral circuit n
2-3