Remc3 Data Bit Counter Register - Epson Arm S1C31 Series Technical Manual

Before the counter can start counting by this bit, the REMC3DBCTL.MODEN bit must be set to 1.
While the counter is running, writing 0 to the REMC3DBCTL.PRUN bit stops count operations.
When the counter stops by occurrence of a compare DB in one-shot mode, this bit is automatically
cleared to 0.
Bits 7–5 Reserved
Bit 4 REMOINV
This bit inverts the REMO output signal.
1 (R/W): Inverted
0 (R/W): Non-inverted
For more information, see Figure 18.4.3.1.
Bit 3 BUFEN
This bit enables or disables the compare buffers.
1 (R/W): Enable
0 (R/W): Disable
For more information, refer to "Continuous Data Transmission and Compare Buffers."
Note: The REMC3DBCTL.BUFEN bit must be set to 0 when setting the data signal duty and cycle
for the first time.
Bit 2 TRMD
This bit selects the operation mode of the 16-bit counter for data signal generation.
1 (R/W): One-shot mode
0 (R/W): Repeat mode
For more information, refer to "REMO Output Waveform, Data signal."
Bit 1 REMCRST
This bit issues software reset to the REMC3.
1 (W): Issue software reset
0 (W): Ineffective
1 (R): Software reset is executing.
0 (R): Software reset has finished. (During normal operation)
Setting this bit resets the REMC3 internal counters and interrupt flags. This bit is automatically
cleared after the reset processing has finished.
Note: After the data signal is output in one-shot mode, set the REMC3DBCTL.REMCRST bit to 1.
Bit 0 MODEN
This bit enables the REMC3 operations.
1 (R/W): Enable REMC3 operations (The operating clock is supplied.)
0 (R/W): Disable REMC3 operations (The operating clock is stopped.)
Note: If the REMC3DBCTL.MODEN bit is altered from 1 to 0 while sending data, the data being
sent cannot be guaranteed. When setting the REMC3DBCTL.MODEN bit to 1 again after that,
be sure to write 1 to the REMC3DBCTL.REMCRST bit as well.

REMC3 Data Bit Counter Register

Register name Bit
REMC3DBCNT 15–0 DBCNT[15:0]
Bits 15–0 DBCNT[15:0]
The current value of the 16-bit counter for data signal generation can be read out through these bits.
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
Bit name Initial
0x0000
Seiko Epson Corporation
18 IR REMOTE CONTROLLER (REMC3)
Reset R/W
H0/S0 R Cleared by writing 1 to the
REMC3DBCTL.REMCRST bit.
Remarks
18-9