Table of Contents
Advertisement
15 Quad Synchronous Serial Interface (QSPI)
If an address in the memory mapped access area that is not continuous to the previous read address is read, the
HREADY signal is pulled down to low immediately and the FIFO read level is cleared to 0 (empty status). The
#QSPISSn signal is negated once for the period set in the QSPI_nMMACFG1.TCSH[3:0] bits and then asserted
again. After that a new address cycle, dummy cycle, and data cycle are executed.
The beginning and the end of each address, dummy, or data cycle take a couple of HCLK clocks for handshak-
ing.
HCLK
HSEL
HADDR
HTRANS
HSIZE
HREADY
HRDATA
fifo_read_level
QSPI_nMOD register
CPOL bit
CPHA bit
1
1
QSPICLKn
0
0
QSDIOn[3:0]
HCLK
HSEL
HADDR
HTRANS
HSIZE
HREADY
HRDATA
fifo_read_level
QSPI_nMOD register
CPOL bit
CPHA bit
1
1
QSPICLKn
0
0
QSDIOn[3:0]
Figure 15.5.6.1 Data Receiving Operation in Memory Mapped Access Mode - First 32-bit Read
15-18
n
2
2
Address cycle
(high-order 8/16 bits)
0
Dummy cycle
Data cycle 1
Seiko Epson Corporation
0
Address cycle
(low-order 16 bits)
n
1
0
Data cycle 2
Data cycle 3
(prefetching)
(prefetching)
S1C31D41 TECHNICAL MANUAL
Dummy
cycle
1
2
(Rev. 1.1)
Advertisement
Table of Contents
