P Port Clock Control Register - Epson Arm S1C31 Series Technical Manual

7 I/O PORTS (PPORT)

P Port Clock Control Register

Register name Bit
PPORTCLK 15–9 –
8
7–4 CLKDIV[3:0]
3–2 KRSTCFG[1:0]
1–0 CLKSRC[1:0]
Bits 15–9 Reserved
Bit 8 DBRUN
This bit sets whether the PPORT operating clock is supplied during debugging or not.
1 (R/WP): Clock supplied during debugging
0 (R/WP): No clock supplied during debugging
Bits 7–4 CLKDIV[3:0]
These bits select the division ratio of the PPORT operating clock (chattering filter clock).
Bits 3–2 KRSTCFG[1:0]
These bits configure the key-entry reset function.
PPORTCLK.KRSTCFG[1:0] bits
Bits 1–0 CLKSRC[1:0]
These bits select the clock source of PPORT (chattering filter).
The PPORT operating clock should be configured by selecting the clock source using the PPORT-
CLK.CLKSRC[1:0] bits and the clock division ratio using the PPORTCLK.CLKDIV[3:0] bits as
shown in Table 7.6.3. These settings determine the input sampling time of the chattering filter.
PPORTCLK.CLKDIV[3:0]
bits
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
(Note) The oscillation circuits/external input that are not supported in this IC cannot be
selected as the clock source.
7-10
Bit name Initial
0x00
DBRUN 0
0x0
0x0
0x0
Table 7.6.2 Key-Entry Reset Function Settings
0x3
0x2
0x1
0x0
Table 7.6.3 Clock Source and Division Ratio Settings
0x0
IOSC
Seiko Epson Corporation
Reset R/W
– R –
H0 R/WP
H0 R/WP
H0 R/WP
H0 R/WP
key-entry reset
Reset when P0[3:0] inputs = all low
Reset when P0[2:0] inputs = all low
Reset when P0[1:0] inputs = all low
Disable
PPORTCLK.CLKSRC[1:0] bits
0x1 0x2
OSC1 OSC3
1/32,768
1/16,384
1/8,192
1/4,096
1/2,048
1/1,024
1/512
1/256
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
Remarks
0x3
EXOSC
1/1
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)