Epson Arm S1C31 Series Technical Manual page 196

fifo_read_level
QSPI_nMOD register
CPOL bit CPHA bit
1 1
QSPICLKn
0 0
QSDIOn[3:0]
Figure 15.5.6.2 Data Receiving Operation in Memory Mapped Access Mode - 32-bit Sequential Read
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
HCLK
HSEL
HADDR
n
HTRANS
HSIZE
HREADY
HRDATA
2
Seiko Epson Corporation
15 Quad Synchronous Serial Interface (QSPI)
n+4 n+8
2
2
n n+4
1 0
Data cycle
(for n+8)
n+8
1 0
Data cycle
(prefetching)
15-19