Clg Iosc Control Register; Clg Osc1 Control Register - Epson Arm S1C31 Series Technical Manual

CLG IOSC Control Register

Register name Bit
CLGIOSC 15–8 –
7–2 –
1–0 IOSCFQ[1:0]
Bits 15–2 Reserved
Bits 1–0 IOSCFQ[1:0]
These bits select the IOSCCLK frequency.
IOSCFQ[1:0] bits

CLG OSC1 Control Register

Register name Bit
CLGOSC1 15
14
13
12
11
10–8 CGI1[2:0]
7–6 INV1B[1:0]
5–4 INV1N[1:0]
3–2 –
1–0 OSC1WT[1:0]
Bit 15 Reserved
Bit 14 OSDRB
This bit enables the OSC1 oscillator circuit restart function by the oscillation stop detector when
OSC1 oscillation stop is detected.
1 (R/WP): Enable (Restart the OSC1 oscillator circuit when oscillation stop is detected.)
0 (R/WP): Disable
Bit 13 OSDEN
This bit controls the oscillation stop detector in the OSC1 oscillator circuit.
1 (R/WP): OSC1 oscillation stop detector on
0 (R/WP): OSC1 oscillation stop detector off
Note: Do not write 1 to the CLGOSC1.OSDEN bit before stabilized OSC1CLK is supplied.
Furthermore, the CLGOSC1.OSDEN bit should be set to 0 when the CLGOSC.OSC1EN bit
is set to 0.
Bit 12 OSC1BUP
This bit enables the oscillation startup control circuit in the OSC1 oscillator circuit.
1 (R/WP): Enable (Activate booster operation at startup.)
0 (R/WP): Disable
Bit 11 OSC1SELCR
This bit selects an oscillator type of the OSC1 oscillator circuit.
1 (R/WP): Internal oscillator
0 (R/WP): Crystal oscillator
Bits 10–8 CGI1[2:0]
These bits set the internal gate capacitance in the OSC1 oscillator circuit.
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
Bit name Initial
0x00
0x00
0x2
Table 2.6.4 IOSCCLK Frequency Selection
CLGIOSC.
V voltage mode = mode0
D1
0x3 Reserved
0x2
0x1 2.0 MHz
0x0 1.0 MHz
Bit name Initial
–
OSDRB
OSDEN
OSC1BUP
OSC1SELCR
0x0
0x2
0x1
0x0
0x2
Seiko Epson Corporation
2 POWER SUPPLY, RESET, AND CLOCKS
Reset R/W
– R –
– R
H0 R/WP
IOSCCLK frequency
V voltage mode = mode1
D1
Setting prohibited
8 MHz
1.8 MHz
0.9 MHz
Reset R/W
0 – R –
1 H0 R/WP
0 H0 R/WP
1 H0 R/WP
0 H0 R/WP
H0 R/WP
H0 R/WP
H0 R/WP
– R
H0 R/WP
Remarks
Remarks
2-19