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5 INTERRUPT
For specific information on causes of interrupts, interrupt flags, and interrupt enable bits, refer to the respective pe-
ripheral circuit descriptions.
Note: To prevent occurrence of unnecessary interrupts, the corresponding interrupt flag should be
cleared before setting the interrupt enable bit to 1 (interrupt enabled) and before terminating the
interrupt handler routine.
5.4 NMI
The watchdog timer embedded in this IC can generate a non-maskable interrupt (NMI). This interrupt takes prece-
dence over other interrupts and is unconditionally accepted by the CPU.
For detailed information on generating NMI, refer to the "Watchdog Timer" chapter.
5-4
Seiko Epson Corporation
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
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