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4 MEMORY AND BUS
Bit 0
CACHEEN
This bit enables the instruction cache function.
1 (R/W): Enable instruction cache
0 (R/W): Disable instruction cache
FLASHC Flash Read Cycle Register
Register name
Bit
FLASHCWAIT
15–9 –
8
7–2 –
1–0 RDWAIT[1:0]
Bits 15–2 Reserved
Bits 1–0
RDWAIT[1:0]
These bits set the number of bus access cycles for reading from the Flash memory.
Table 4.8.1 Setting Number of Bus Access Cycles for Flash Read
FLASHCWAIT.
RDWAIT[1:0] bits
0x3
0x2
0x1
0x0
Notes: • Be sure to set the FLASHCWAIT.RDWAIT[1:0] bits before the system clock is configured.
• When the FLASHCWAIT.RDWAIT[1:0] bit setting is altered from 0x2 to 0x1, add two NOP
instructions immediately after that.
Program example: FLASHC->WAIT_b.RDWAIT = 1;
4-10
Bit name
Initial
0x00
(reserved)
0
0x00
0x1
Number of bus
access cycles
4
3
2
1
asm("NOP");
asm("NOP");
CLG->OSC_b.IOSCEN = 0;
Seiko Epson Corporation
Reset
R/W
–
R
–
H0
R/WP
–
R
H0
R/WP
System clock frequency
PWGACTL.
PWGACTL.
REGSEL bit = 0
REGSEL bit = 1
2.1 MHz (max.)
16.3 MHz (max.)
1.02 MHz (max.)
8.4 MHz (max.)
S1C31D41 TECHNICAL MANUAL
Remarks
(Rev. 1.1)
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