Revision History - Epson Arm S1C31 Series Technical Manual

Revision History

Code No. Page
414190500 All New establishment
414190501 1-3 1.1 Features
Added the following annotation to Table 1.1.1.
*2 SLEEP mode refers to deep sleep mode in the Cortex
2-14 2.4.2 Transition between Operating Modes
SLEEP mode
Added the following description:
The RAM retains data even in SLEEP mode.
4-2 4.3.1 Flash Memory Pin
Deleted the following description:
For the V
the "Electrical Characteristics" chapter.
7-6 7.4.2 Port Input/Output Control
Chattering filter function
The equation number was corrected.
(Eq. 6.2) → (Eq. 7.2)
15-1 15.1 Overview
Corrected the description.
- 1M-byte external Flash memory mapped access area that allows programmable re-mapping.
Added an item to Table 15.1.1.
Memory mapped access area for external Flash memory: 1M-byte area beginning with address
0x0004_0000
15-8, 9 15.4 Data Format
Figures 15.4.1 and 15.4.2
Added the following bit setting:
QSPI_nMOD.CHDL[3:0] bits = 0x7
Figure 15.4.3
Added the following bit setting:
QSPI_nMOD.CHDL[3:0] bits = 0x3
15-10, 11 15.5.2 Memory Mapped Access Mode
Figures 15.5.2.1 and 15.5.2.2
Corrected the description.
The QSPI treats the dummy cycle as 6 cycles including 1 driving cycle.
The QSPI treats the data cycle as 2 cycles including 2 driving cycles.
15-11 15.5.2 Memory Mapped Access Mode
Corrected the description.
The memory mapped access area for external Flash memory in the system memory area is used to map
the external Flash memory and to access from the CPU.
15-17 15.5.6 Data Reception in Memory Mapped Access Mode
Data receiving procedure
Corrected the description.
4. Read the memory mapped access area for external Flash memory with an 8, 16, or 32-bit memory
15-29 15.8 Control Registers
QSPI Ch.n Mode Register
Deleted the following description of the CHDL[3:0] bits:
This setting is required to output the XIP confirmation bit to Micron Flash memories or to output the
mode byte to Spansion Flash memories.
15-35 15.8 Control Registers
QSPI Ch.n Memory Mapped Access Configuration Register 2
Modified the register table.
DUMDL[3:0], DUMLN[3:0]: Initial = 0x0 → 0x7
15-37 15.8 Control Registers
QSPI Ch.n Mode Byte Register
Added the following description to the XIPEXT[7:0] bits:
However, set these bits as follows when the HW processor (HWP) is used:
• Before enabling the HWP, set to the same value as the QSPI_nMB.XIPACT[7:0] bits.
• Before disabling the HWP, set to the mode byte for terminating the XIP session.
in SLEEP mode.
voltage, refer to "Recommended Operating Conditions, Flash programming voltage V
PP
(QSPI_nMMACFG2.DUMDL[3:0] bits = 0x0, QSPI_nMMACFG2.DUMLN[3:0] bits = 0x5)
(QSPI_nMOD.CHDL[3:0] bits = 0x1, QSPI_nMOD.CHLN[3:0] bits = 0x1)
read instruction.
This operation directly reads data within the 1M-byte external Flash memory area remapped to the
memory mapped access area for external Flash memory at Step 2.
Contents
® -M0+ processor. The RAM retains data even
REVISION HISTORY
" in
PP