Sdac2 Clock Control Register; Sdac2 Control Register - Epson Arm S1C31 Series Technical Manual

Bit 0 HWP0TRG
This bit starts executing the command specified by the HWP internal register.
1 (W): Trigger to issue command
0 (W): Setting prohibited
1 (R): In command issuing process
0 (R): Command issuance completed/standby to issue command

SDAC2 Clock Control Register

Register name Bit
SDAC2CLK 15–9 –
8
7–6 –
5–4 CLKDIV[1:0]
3–2 –
1–0 CLKSRC[1:0]
Bits 15–9 Reserved
Bit 8 DBRUN
This bit sets whether the SDAC2 operating clock is supplied in DEBUG mode or not.
1 (R/W): Clock supplied in DEBUG mode
0 (R/W): No clock supplied in DEBUG mode
Bits 7–6 Reserved
Bits 5–4 CLKDIV[1:0]
These bits select the division ratio of the SDAC2 operating clock.
Bits 3–2 Reserved
Bits 1–0 CLKSRC[1:0]
These bits select the clock source of SDAC2.
SDAC2CLK.
CLKDIV[1:0] bits
0x3
0x2
0x1
0x0
(Note) The oscillation circuits/external input that are not supported in this IC cannot be
selected as the clock source.
Note: The SDAC2CLK register settings can be altered only when the SDAC2CTL.SDACEN bit = 0.

SDAC2 Control Register

Register name Bit
SDAC2CTL 15–8 –
7–4 –
3
2
1
0
Bits 15–4 Reserved
Bit 3 TONEON
This bit enables the square-wave tone generator.
1 (R/W): Turn on square-wave tone
0 (R/W): Turn off square-wave tone
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
Bit name Initial
0x00
DBRUN 0
0x0
0x0
0x0
0x0
Table 22.7.1 Clock Source and Division Ratio Settings
0x0
IOSC
Reserved
1/4
1/2
1/1
Bit name Initial
0x00
0x00
TONEON 0
– 0
RESAMPEN 0
SDACEN 0
Seiko Epson Corporation
22 HW Processor (HWP) and Sound Output (SDAC2)
Reset R/W
– R –
H0 R/W
– R
H0 R/W
– R
H0 R/W
SDAC2CLK.CLKSRC[1:0] bits
0x1 0x2
OSC1 OSC3
Reserved
1/4
Reserved
1/2
1/1
Reset R/W
– R –
– R
H0 R/W
– R
H0 R/W
H0 R/W
Remarks
0x3
EXOSC
Reserved
1/4
1/2
1/1
Remarks
22-29