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Bit 3
ERR1IF
Bit 2
DATREQ1IF
Bit 1
ERR0IF
Bit 0
DATREQ0IF
These bits indicate the SDAC2 interrupt cause occurrence status.
1 (R):
Cause of interrupt occurred
0 (R):
No cause of interrupt occurred
1 (W):
Clear flag
0 (W):
Ineffective
The following shows the correspondence between the bit and interrupt:
SDAC2INTF.ERR1IF bit:
SDAC2INTF.DATREQ1IF bit: Ch.1 data request interrupt
SDAC2INTF.ERR0IF bit:
SDAC2INTF.DATREQ0IF bit: Ch.0 data request interrupt
Note: This register is used by the HWP. Do not write any data to this register while the HWP operation
is enabled (HWPCTL.HWPEN bit = 1).
SDAC2 Interrupt Enable Register
Register name
Bit
SDAC2INTE
15–8 –
7–2 –
3
2
1
0
Bits 15–4 Reserved
Bit 3
ERR1IE
Bit 2
DATREQ1IE
Bit 1
ERR0IE
Bit 0
DATREQ0IE
These bits enable SDAC2 interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
The following shows the correspondence between the bit and interrupt:
SDAC2INTE.ERR1IE bit:
SDAC2INTE.DATREQ1IE bit: Ch.1 data request interrupt
SDAC2INTE.ERR0IE bit:
SDAC2INTE.DATREQ0IE bit: Ch.0 data request interrupt
Note: This register is used by the HWP. Do not write any data to this register while the HWP operation
is enabled (HWPCTL.HWPEN bit = 1).
SDAC2 Resampler Rate Register
Register name
Bit
SDAC2RESAMP
15–11 –
10–0 RESAMPRATE[10:0]
Bits 15–11 Reserved
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
Ch.1 error occurrence interrupt
Ch.0 error occurrence interrupt
Bit name
Initial
0x00
0x00
ERR1IE
0
DATREQ1IE
0
ERR0IE
0
DATREQ0IE
0
Ch.1 error occurrence interrupt
Ch.0 error occurrence interrupt
Bit name
Initial
0x00
0x400
Seiko Epson Corporation
22 HW Processor (HWP) and Sound Output (SDAC2)
Reset
R/W
–
R
–
–
R
H0
R/W
H0
R/W
H0
R/W
H0
R/W
Reset
R/W
–
R
–
H0
R/W
Remarks
Remarks
22-31
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