Table of Contents
Advertisement
22.6.2 Memory Check Function Register
Function ID Register
Register name
Bit
FUNCTION
15–8 –
7–0 ID[7:0]
Bits 15–8 Reserved
Set to 0x00 when writing data to this register.
Bits 7–0
ID[7:0]
These bits select the function to be executed in the HWP. (Refer to Table 22.6.1.1.)
Set to 0x03 when executing the Memory Check function.
Interrupt Mask Register
Register name
Bit
INTMASK
15–8 –
(Memory Check)
7–2 –
1
0
Bits 15–2 Reserved
Set to 0x000(0) when writing data to this register.
Bit 1
TO_PROCESSING
Bit 0
TO_IDLE
These bits set whether the interrupt request when a state transition occurs during executing the Memo-
ry Check function is enabled or not.
1 (W):
Mask interrupt (disabled)
0 (W):
Enable interrupt
For more information on the state transition interrupts that can be masked with these bits, refer to
Table 22.5.2.
Memory Address Register
Register name
Bit
MEMADDR
31–0 ADDRESS[31:0]
(Memory Check)
Bits 31–0 ADDRESS[31:0]
These bits specify the memory check start address.
The address should be specified within the range shown below.
In case of RAM:
0x15 0000, ..., 0x15 1fff
0x15 3000, ..., 0x15 67ff
In case of internal Flash:
0x00 0000, ..., 0x02 ffff
In case of external QSPI-Flash:
0x00 0000 + OFFSET, ..., 0x0f ffff + OFFSET
* The OFFSET is 0x04 0000, the start address of the memory mapped access area for external Flash
memory (refer to "Figure 4.1.1 Memory Map").
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
Bit name
Initial
x
x
Bit name
Initial
x
x
TO_PROCESSING
x
TO_IDLE
x
Bit name
Initial
x
Seiko Epson Corporation
22 HW Processor (HWP) and Sound Output (SDAC2)
Reset
R/W
–
R/W
–
–
R/W
Reset
R/W
–
R/W
–
–
R/W
–
R/W
–
R/W
Reset
R/W
–
R/W
–
Remarks
Remarks
Remarks
22-25
Advertisement
Table of Contents
