Appendix A List Of Peripheral Circuit Control Registers; System Register (Sys); Power Generator (Pwga) - Epson Arm S1C31 Series Technical Manual

Appendix A List of Peripheral Circuit
0x0020 0000
Address Register name
0x0020 SYSPROT
0000 (System
Protect Register)
0x0020 0020
Address Register name
0x0020 PWGACTL
0020
(PWGA Control
Register)
0x0020 0040–0x0020 005a
Address Register name
0x0020 CLGSCLK
0040
(CLG System Clock
Control Register)
0x0020 CLGOSC
0042
(CLG Oscillation
Control Register)
0x0020 CLGIOSC
0044 (CLG IOSC Control
Register)
0x0020 CLGOSC1
0046
(CLG OSC1 Control
Register)
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)

APPENDIX A LIST OF PERIPHERAL CIRCUIT CONTROL REGISTERS

Control Registers
Bit Bit name
15–0 PROT[15:0]
Bit Bit name
15–8 –
7–6 –
5 REGDIS
4 REGSEL
3–2 –
1–0 REGMODE[1:0]
Bit Bit name
15 WUPMD
14 –
13–12 WUPDIV[1:0]
11–10 –
9–8 WUPSRC[1:0]
7–6 –
5–4 CLKDIV[1:0]
3–2 –
1–0 CLKSRC[1:0]
15–12 –
11 EXOSCSLPC
10 OSC3SLPC
9 OSC1SLPC
8 IOSCSLPC
7–4 –
3 EXOSCEN
2 OSC3EN
1 OSC1EN
0 IOSCEN
15–8 –
7–2 –
1–0 IOSCFQ[1:0]
15 –
14 OSDRB
13 OSDEN
12 OSC1BUP
11 OSC1SELCR
10–8 CGI1[2:0]
7–6 INV1B[1:0]
5–4 INV1N[1:0]
3–2 –
1–0 OSC1WT[1:0]
Seiko Epson Corporation

System Register (SYS)

Initial Reset R/W
0x0000 H0 R/W

Power Generator (PWGA)

Initial Reset R/W
0x00 – R
0x0 – R
0 H0 R/WP
1 H0 R/WP
0x0 – R
0x0 H0 R/WP
Clock Generator (CLG)
Initial Reset R/W
0 H0 R/WP –
0 – R
0x0 H0 R/WP
0x0 – R
0x0 H0 R/WP
0x0 – R
0x2 H0 R/WP
0x0 – R
0x0 H0 R/WP
0x0 – R
1 H0 R/W
1 H0 R/W
1 H0 R/W
1 H0 R/W
0x0 – R
0 H0 R/W
0 H0 R/W
0 H0 R/W
1 H0 R/W
0x00 – R
0x00 – R
0x2 H0 R/WP
0 – R
1 H0 R/WP
0 H0 R/WP
1 H0 R/WP
0 H0 R/WP
0x0 H0 R/WP
0x2 H0 R/WP
0x1 H0 R/WP
0x0 – R
0x2 H0 R/WP
Remarks
–
Remarks
–
Remarks
–
–
–
AP-A-1