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Input
DPSY01 (Function ID: 511001)
From DPSY02
511001 8B02021E48
DPSY02_OEC_RCV
SYNCHK2 (Function ID: 560001)
From SYNCHK2
560001 850B021F59
SYNC02_SYN_CLC
SYNCHK_Ry (Function ID: 561081)
From SYNCHK_Ry1
ΔV1
SyncRy1-dV
On
Δf1
SyncRy1-df
SyncRy1-dfEN
SyncRy1-dƟ
ΔƟ1
ΔƟ1≈0
SyncRy1-Ɵ≈0
ΔƟ1 less
SyncRy1-Ɵ less
From SYNCHK_Ry2
ΔV2
SyncRy2-dV
On
Δf2
SyncRy2-df
SyncRy2-dfEN
ΔƟ2
SyncRy2-dƟ
SyncRy2-Ɵ≈0
ΔƟ2≈0
SyncRy2-Ɵ less
ΔƟ2 less
PLC signals for relay selection relating to SYNCHK2
560001 800B02EDED
SYNC02_RY1_USE_STS
560001 800B02EDEE
SYNC02_RY2_USE_STS
PLC signals importation from external conditions
560001 800B02EDE2
SYNC02_SCL_F_ECP
560001 800B02EDE6
SYNC02_LPS_CL_ECP
560001 800B02EDE5
SYNC02_SPS_CL_ECP
560001 800B02EDE1
SYNC02_SBP_SSP
Figure 4.5-15 Synchronization check logic in SYNCHK2
Check logic and settings for synchronous network
(ii)
As shown in Figure 4.5-14, the ∆V, ∆θ, and ∆f signals are required to check the synchronous
condition; the three signals are input to the logic. The sync-success signal "SYNC01_SYN_CLC"
is provided after the operation of the delay timer "SYNC01_TSYN". The user can regulate the
timer using the setting [SYNC01_TSYN].
Check logic and settings for asynchronous network
(iii)
In Figure 4.5-14, the '∆θ1≈0' and '∆θ1_less' signals are used to check the synchronization
condition when the user sets On for scheme switch [SYNC01-Split_SYN_EN]; subsequently
sequentially the sync-success signal "SYNC01_SYN_CLC" is issued for the DPSY01 function.
Bypassing synchronization check
(iv)
If the user wishes to remove the synchronization check, set Off for the scheme switch [SYNC01-
SYNCHK1EN]. The DPSY01 function can operate with the absence of the sync-success signal
Close command (Operate)
SYNCHK2 (Function ID: 560001)
&
&
&
&
Check for synchronous network
&
≥
&
≥
&
≥
&
&
&
Check for asynchronous network
≥
≥
Bypassing condition
Off
SYNC02-SYNCHK2EN
- 611 -
SYNCHK logic in SYNCHK2
SYNC02_SCK_CS16
560001 880B021F6E
SYNC02_TSYN2
SYNC02_SCK_CS01
t
0
560001 840B021F5F
&
&
1
0.0 to 1800.0s
SYNC02_SCK_CS04
560001 870B021F62
SYNC02_SCK_CS09
&
560001 8C0B021F67
&
SYNC02_SCK_CS03
560001 860B021F61
&
SYNC02_SCK_CS02
560001 850B021F60
&
SYNC02_Ry_Ang_0Time
560001 870B021F77
&
SYNC02_Ry_Ang_RDC
560001 880B021F78
&
On
SYNC02-Split_SYN_EN
560001 800B02EDEB
6F2T0207 (0.01)
SYNC02_LPS_CLC
≥
560001 890B021F53
SYNC02_TSYN
t
0
0.0 to 100.0s
SYNC02_SPS_CLC
5600018 D0B021F51
&
SYNC02_SBK_CSP
1
Blocking
GRE200 (5,6)
Output
560001 820B021F56
SYNC02_SCL_F
Sync Failed
To DPSY02
560001 850B021F59
SYNC02_SYN_CLC
&
Sync success
560001 800B021F54
SYNC02_SBP
Sync bypass
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