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detection can be characterized with Hysteresis setting [Swl-HYST] (default=2%). Note the
swell stage is detected when all phase-to-phase voltage are twisted at the same time.
0019001E70
V1ab_SWL_INS
0019031E70
V1bc_SWL_INS
0019061E70
V1ca_SWL_INS
0019121E70
V3_SWL_INS
Sagging/Dipping stages
If the amplitude is lower than the nominal (<100%), SAG logic can signal a sagging detection
signal together with three sag stages.
Setting [Dip-ALRM] defines an alarm level (default=80%); the detection is characterized with
Hysteresis setting [Dip-HYST]=2%. The user can delay issuing alarms with the timer setting
[Dip-CONFT].
8419301EB3
S
&
V1ab_SWL_ST1
R
1
8519301EB4
S
V1bc_SWL_ST1
R
1
8619301EB5
S
V1ca_SWL_ST1
R
1
8419901EB3
S
V3_SWL_ST1
R
1
Figure 4.3-5 Swell detection logic
- 559 -
t
0
S
R
0.6s
1
t
0
0.3s
≥1
8719301EB6
V1M_SWL_STAGE1
t
0
S
R
0.6s
1
t
0
0.3s
≥1
8719901EB6
V3M_SWL_STAGE1
6F2T0207 (0.01)
8919301EB7
V1_SWL_STAGE2
8B19301EB8
V1_SWL_BLOCK
8D19301EB9
S
V1_SWL_STAGE3
R
0.1s
8F19301EBA
&
V1_SWL_DETECTED
1
8919901EB7
V3_SWL_STAGE2
8B19901EB8
V3_SWL_BLOCK
8D19901EB9
S
V3_SWL_STAGE3
R
0.1s
8F19901EBA
&
V3_SWL_DETECTED
1
GRE200 (5,6)
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