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800000EBB2
EXT.ARC_START
From TRC
GEN.TRIP
ARC SHOT OVER
Start-up logic
ARC READY
Start-up logic
Start-up logic
ARC=ON
800000EBB3
ARC NO ACT
Shot counter logic
SHOT_1ST
From reset point
ARC RS
When the input signals 'ARC_START', 'SHOT_1ST' and 'ARC READY' are active at the
same time, a flip-flop circuit issues the 'ARC IN-PROG' signal. The signals 'ARC IN-PROG'
and 'ARC_START' will be issued when the 'SHOT_1ST' shot is issued from the Shot counter
logic.
SHOT1 logic - settings
(iii)
Figure 2.22-5 shows the SHOT1 logic, which is used for issuing the first reclosing command.
As shown in Figure 2.22-2, the 'ARC SHOT1' signal is generated by the reception of the 'ARC-
S1 IN-PROG' signal from a flip-flop triggered by the signals 'ARC_START' and 'ARC IN-PROG'.
The user is required to provide settings for the [TSHOT] and [TRR] timers for this logic, as
previously discussed in Chapter 2.22.2 (incidentally, a setting for [TSHOT_SUB] may be
required when a user PLC program is accommodated).
From VCHK‡
ARC-VCHK
Always '1' †
ARC-S1 IN-PROG
Flip-flop
Signal generated by the
user's PLC programing
Signal generated by the
user's PLC programing
†Note: As a default, a Logic '1' signal (Always high(TRUE)) is applied at the PLC
connection point 'ARC_MAIN_START'.
‡Note: 'ARC-VCHK' signal enters via the PLC connection point 'ARC_MAIN_COND', as
&
&
1
≥1
0.01s
&
1
Figure 2.22-4 Initiation logic
800000EBB6
ARC_MAIN_COND
800000EBB5
ARC_MAIN_START
810000EBB7
ARC_SUB_START
810000EBB8
ARC_SUB_COND
Figure 2.22-5 SHOT1 logic
- 240 -
&
&
S
R
1
8000001BB6
TSHOT
8000001BB5
t
0
&
&
0.01 – 300.00 s
TRR
t
0
0.01 – 310.00 s
TSHOT_SUB
t
0
&
8100001BB7
0.01 – 300.00 s
&
8100001BB8
6F2T0207 (0.01)
8100001B60
EXT_START_SIGNAL
1
&
To Final trip stage
ARC UNREADY
ARC SHOT_1ST
SHOT NUMBER OVER
ARC_START
To ARC SHOT1 logic
8000001B61
To ARC SHOT2 logic
ARC_START
8200001B64
ARC IN-PROG
To Shot counter logic
ARC NOT_IN-PROG
To Issuing command logic
8000001B65
ARC SHOT1
≥1
To Final trip stage
ARC-S1 TRR
GRE200 (5,6)
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