ABB Relion Technical Manual page 343

1MRK 502 048-UUS A
Technical manual
DVDI Detection
DVDI detection Phase 1
IA
DIPU
VA
DVPU
a
b
VPPU
IB
DVDI detection Phase 2
VB
IC
DVDI detection Phase 3
VC
VA
a
a<b
b
IA
a
a>b
b
50P
52A
VB
a
a<b
b
IB
a
a>b
b
VC
a
a<b
b
IC
a
a>b
b
ANSI10000034 V2 EN
Figure 158: Simplified logic diagram for DV/DI detection part
Secondary system supervision
One cycle
delay
|DI|
One cycle
delay
|DV|
a>b 20 ms 1.5 cycle
0 0
Same logic as for phase 1
Same logic as for phase 1
AND
OR
AND
OR
AND
OR
AND
OR
AND
OR
AND
OR
Section 11
a
a>b
b
a
a>b
AND
b
AND
AND
AND
FuseFailDetDVDI
OR
ANSI10000034-2-en.vsd
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