Mitsubishi Electric Q26UD(E)HCPU User Manual page 475

Number Name
OFF: Comment read
Comment read
SM720
completion flag ON: Comment read
OFF: File not accessed
File being
SM721 ON: File being
accessed
OFF: Error detection
BIN/DBIN
SM722 instruction error
ON: Error detection
disabling flag
OFF: Not executed by
XCALL instruction
SM734 execution condition
ON: Executed by
designation
Meaning Explanation
This relay turns on only during first scan
after the processing of the COMRD or
PRC instruction is completed.
not completed
This relay turns on only during first scan
completed
after the processing of the COMRD
instruction is completed.
This relay is on while a file is being
accessed by the SP.FWRITE,
SP.FREAD, COMRD, PRC, or LEDC
instruction.
This relay is on while a file is being
accessed by the SP.FWRITE,
SP.FREAD, COMRD, or LEDC
instruction.
This relay is on while a file is being
accessed by the SP.FWRITE,
SP.FREAD, COMRD, or SP.DEVST
instruction.
• This relay is on while a file is being
accessed by the SP.FWRITE,
SP.FREAD, COMRD, or SP.DEVST
instruction.
• This relay is on while the standard
ROM is being accessed.
• This relay is on while the
S(P).SFCSCOMR or
S(P).SFCTCOMR instruction is being
executed.
accessed
• This relay is on while a file is being
accessed by the SP.FWRITE,
SP.FREAD, COMRD, or SP.DEVST
instruction.
• This relay is on while a SD memory
card or the standard ROM is being
accessed.
• This relay is on while the
S(P).SFCSCOMR or
S(P).SFCTCOMR instruction is being
executed.
This relay is on while an ATA card or the
standard ROM is being accessed.
This relay is on while the
S(P).SFCSCOMR or S(P).SFCTCOMR
instruction is being executed.
This relay is on while the SP.FTPPUT or
SP.FTPGET instruction is being
executed.
Turned ON when "OPERATION ERROR"
performed
is suppressed for BIN or DBIN
instruction.
not performed
• During OFF, XCALL instructions will
execution not be executed even if execution
condition risen condition is risen.
• During ON, XCALL instructions will be
execution executed when execution condition is
condition risen risen.
Corresponding
Set by Corresponding
ACPU
(When Set)
M9
S (Status
New
change)
S (Status
New
change)
U New
U New
APPENDICES
A
CPU
Qn(H)
QnPH
QnPRH
QnU
LCPU
Qn(H)
QnPH
Qn(H)
QnPH
QnPRH
QnU
QnUDV
LCPU
*4
QnU
*11
QnU
*17
LCPU
QCPU
LCPU
*4
Qn(H)
473