Mitsubishi Electric Q26UD(E)HCPU User Manual page 563

Special Special
ACPU
register register
special
after after
register
conversion modification

D9002 SD1002
D9005 SD1005 -
D9008 SD1008 SD0
D9009 SD1009 SD62
D9010 SD1010 

D9011 SD1011
D9014 SD1014 
D9015 SD1015 SD203
Name Meaning
I/O module verify
I/O module
error module
verify error
number
AC DOWN Number of times
counter for AC DOWN
Self-
Self-diagnostic
diagnostic
error number
error
F number at which
Annunciator
external failure has
detection
occurred
Step number at
which operation
error has occurred.
Error step
Step number at
which operation
error has occurred.
I/O control I/O control mode
mode number
Operating
Operating status of
status of
CPU
CPU
Explanation
• If the status of the I/O modules changes from that
obtained at power-on, the lowest first I/O number of the
module is stored in hexadecimal. (Example: If a module
verification error is occurred on the output module with
output numbers Y50 to Y6F, "50" is stored in
hexadecimal.) To monitor the number by a programming
tool, monitor in hexadecimal. (This register is cleared
when contents in SD1116 to SD1123 are all reset to "0".)
• I/O module verification is conducted on I/O modules on
remote I/O stations.
• A value stored in this register is incremented by one
whenever the input voltage falls to or below 85% (AC
power) or 65% (DC power) of the rating during operation
of the CPU module.
• The counter starts the routine: counts up from 0 to 32767,
then counts down to -32768 and then again counts up to
0.
This register stores the error code of an error detected by
self-diagnostics.
• When any of F0 to F2047 (default device setting) is
turned on by the OUT F or SET F instruction, the F
number that has been detected earliest among the F
numbers that have turned on is stored in BIN code.
• SD1009 can be cleared by RST F or LEDR instruction. If
another F number has been detected, the clearing of
SD1009 causes the next number to be stored in SD1009.
If an operation error occurred during execution of an
application instruction, the number of the step having the
error is stored. The contents of SD1010 are updated upon
every operation error.
If an operation error occurred during execution of an
application instruction, the number of the step having the
error is stored. Because the step number is stored in
SD1011 when SM1011 turns from off to on, the data in
SD1011 are not updated unless SM1011 is cleared by a
user program
The I/O control mode that has been set is returned in any of
the following numbers.
• 0:Both input and output in direct mode
• 1:Input in refresh mode, output in direct mode
• 3:Both input and output in refresh mode
Operation status of a CPU module is stored as shown
below.
b15 to b12 b11 to b8 b7 to b4 b3
Remote RUN/STOP
by computer
0 RUN
STOP
1
*1
2 PAUSE
Status in program
0 Except below
STOP
1
Instruction execution
*1 For the High Performance model QCPU and Process
CPU, if the CPU module is running and SM1040 is off,
the CPU module remains in the RUN status even
though it is set to the PAUSE status.
APPENDICES
Corresponding
CPU
Qn(H)
QnPH
*1
QnU
LCPU
Qn(H)
QnPH
*1
QnU
LCPU
Qn(H)
QnPH
*1
QnU
LCPU
Qn(H)
QnPH
Qn(H)
QnPH
to b0
CPU module switch
0 RUN
Qn(H)
1
STOP
*1
2
PAUSE QnPH
3 STEP RUN
*1
QnU
Remains the same in
LCPU
remote RUN/STOP
mode.
Remote RUN/STOP
by parameter setting
RUN
0
1 STOP
*1
2 PAUSE
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