Mitsubishi Electric Q26UD(E)HCPU User Manual page 566

Special Special
ACPU
register register
special
after after
register
conversion modification

D9050 SD1050

D9051 SD1051
D9052 SD1052 

D9053 SD1053

D9054 SD1054
D9055 SD1055 SD812

D9072 SD1072

D9085 SD1085

D9090 SD1090

D9091 SD1091
D9094 SD1094 SD251
564
Name Meaning
SFC
Error code
program
generated by SFC
error
program
number
Block number
Error block where error
occurred
Step number
Error step where error
occurred
Transition
Error condition number
transition where error
occurred
Error Sequence step
sequence number where
step error occurred
Status latch
Status latch
execution
execution step
step
number
number
Data check of
PLC
serial
communicat
communication
ion check
module
Register for
setting time 1s to 65535s
check value
Microcompu
ter
subroutine Depends on
input data microcomputer
area start package.
device
number
Detailed Self-diagnosis
error code detailed error code
Start I/O
number of Start I/O number of
I/O module I/O module to be
to be replaced
replaced
Explanation
This register stores an error code of the error occurred in
the SFC program.
• 0: No error
• 80: SFC program parameter error
• 81: SFC code error
• 82: Number of steps of simultaneous execution exceeded
• 83: Block start error
• 84: SFC program operation error
This register stores the number of the block in the SFC
program where an error occurred. For error 83, the number
of the block where the program was started is stored.
• This register stores the number of the step in the SFC
program where error 83 occurred.
• For error 80, 81, and 82, "0" is stored.
• For error 83, the block starting step number is stored.
This register stores the number of the transition condition in
the SFC program where error code 84 occurred. For error
codes 80, 81, 82, and 83, "0" is stored.
This register stores the sequence step number of transfer
condition and operation output in the SFC program where
error 84 occurred.
• This register stores the number of the step where a status
latch was executed.
• When a status latch was executed in a main sequence
program, the step No. is stored.
• When a status latch was executed in a SFC program, the
block number and step number are stored.
Block No.
(BIN)
Lower 8 bits
Upper 8 bits
The serial communication module automatically reads and
writes data in a single loopback test to perform
communication check.
Sets the time check time of the data link instructions
(ZNRD, ZNWR) for the MELSECNET/10.
• Setting range: 1s to 65535s (1 to 65535)
• Unit: second
• Default: 10s (If 0 has been set)
For details, refer to the following.
 Manual for respective microcomputer package
This register stores description of the error cause of an
instruction error.
This register stores the first two digits of the start I/O
number of an I/O module, which is to be removed and
mounted online (with power on).
Example) Input module with I/O No. X2F0  H2F
Corresponding
CPU
Qn(H)
QnPH
Qn(H)
QnPH
Qn(H)
QnPH
Qn(H)
QnPH
Qn(H)
QnPH
Qn(H)
QnPH
Step No.
(BIN)
Qn(H)
QnPH
Qn(H)
QnPH
Qn(H)
QnPH
Qn(H)
QnPH
QnU
LCPU
Qn(H)
QnPH
*1