Mitsubishi Electric Q26UD(E)HCPU User Manual page 477

Number Name
Block information
using the multiple
OFF: Block is secured
CPU high-speed
ON: Block set by
SM796 transmission
dedicated
instruction (for
CPU No.1)
Block information
using the multiple
OFF: Block is secured
CPU high-speed
ON: Block set by
SM797 transmission
dedicated
instruction (for
CPU No.2)
Block information
using the multiple
OFF: Block is secured
CPU high-speed
ON: Block set by
SM798 transmission
dedicated
instruction (for
CPU No.3)
Block information
using the multiple
OFF: Block is secured
CPU high-speed
ON: Block set by
SM799 transmission
dedicated
instruction (for
CPU No.4)
*1 Modules whose function version B or later
*2 The following modules support these areas:
• Universal model QCPU whose serial number (first five digits) is "10102" or later
• Q00UJCPU, Q00UCPU, Q01UCPU
*3 The following modules support this area:
• Universal model QCPU whose serial number (first five digits) is "10102" or later
• Q00UCPU, Q01UCPU
*4 Modules whose serial number (first five digits) is "07032" or later
*5 Modules whose serial number (first five digits) is "06082" or later
*6 Modules whose serial number (first five digits) is "07012" or later
*7 Modules whose serial number (first five digits) is "04012" or later
*8 Modules whose serial number (first five digits) is "05032" or later
*9 Universal model QCPU except the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU
*10 Universal model QCPU except the Q00UJCPU
*11 Modules whose serial number (first five digits) is "12052" or later
*12 Modules whose serial number (first five digits) is "14072" or later
*13 Following modules except the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU.
• Modules whose serial number (first five digits) is "14072" or later other than the High-speed Universal model
QCPU
• High-speed Universal model QCPU whose serial number (first five digits) is "16043" or later
*14 Modules whose serial number (first five digits) is "15102" or later
*15 Modules whose serial number (first five digits) is "16042" or later
*16 Modules whose serial number (first five digits) is "16043" or later
*17 Modules whose serial number (first five digits) is "16112" or later
Meaning Explanation
This relay turns on when the number of
the remaining blocks in the dedicated
instruction transmission area used for the
multiple CPU high-speed transmission
dedicated instruction (target CPU= CPU
SD796 cannot be No.1) is less than the number of blocks
secured specified in SD796. This relay is on when
an instruction is executed, and is off while
an END processing is being executed or
when free space is available in the area.
This relay turns on when the number of
the remaining blocks in the dedicated
instruction transmission area used for the
multiple CPU high-speed transmission
dedicated instruction (target CPU= CPU
SD797 cannot be No.2) is less than the number of blocks
secured specified in SD797. This relay is on when
an instruction is executed, and is off while
an END processing is being executed or
when free space is available in the area.
This relay turns on when the number of
the remaining blocks in the dedicated
instruction transmission area used for the
multiple CPU high-speed transmission
dedicated instruction (target CPU= CPU
SD796 cannot be No.3) is less than the number of blocks
secured specified in SD798. This relay is on when
an instruction is executed, and is off while
an END processing is being executed or
when free space is available in the area.
This relay turns on when the number of
the remaining blocks in the dedicated
instruction transmission area used for the
multiple CPU high-speed transmission
dedicated instruction (target CPU= CPU
SD799 cannot be No.) is less than the number of blocks
secured specified in SD799. This relay is on when
an instruction is executed, and is off while
an END processing is being executed or
when free space is available in the area.
Corresponding
Set by Corresponding
ACPU
(When Set)
M9
S
(Instruction
execution/ New
Every END
processing)
S
(Instruction
execution/ New
Every END
processing)
S
(Instruction
execution/ New
Every END
processing)
S
(Instruction
execution/ New
Every END
processing)
APPENDICES
A
CPU
*9
QnU
*9
QnU
*9
QnU
*9
QnU
475