Toshiba GR-200 Series Instruction Manual page 557

Programmable binary input circuits
(ii)
Binary input circuits (BI) can have a pick-up threshold for the input signal. It can be set with
setting [BITH*]. If chattering signals caused by bouncing contacts are coming, circuit filter can
remove the chattering. The filter performance is set with setting [CMP_NUM]. Each binary BI
is constructed with retard and invert logics, so the user can program the circuit with settings
[On Delay Timer], [Off Delay Timer], [INVERSE-SW]; then set On for the respective setting
[BI*_CPL].
Figure 5.6-6 shows binary input circuits, which consists of potential divider, filter, On/Off delay
timer, and inversion logics.
8001001111
From external
(+)
BI1
(–)
8101011111
(+)
BI2
(–)
8201021110
(+)
BI3
(–)
8**********
(+)
(–) BIn
Level_4
R
Level_3
R
Level_2
R
Level_1
R
Figure 5.6-6 Programmable logics of binary input circuits
8001001110
[On Delay Timer]
Filter
BI1-NC BI1
t 0
0.000-300.000s
[INVERSE-SW]
8101011110
[On Delay Timer] [Off Delay Timer]
BI2-NC BI2
t 0
0.000-300.000s
[INVERSE-SW]
8201021110
[On Delay Timer] [Off Delay Timer]
BI3-NC BI3
t 0
0.000-300.000s
[INVERSE-SW]
BI15
[On Delay Timer] [Off Delay Timer]
BI15
BIn-NC
t 0
0.000-300.000s
[INVERSE-SW]
BI
Level_3
[BITH1]
Level_2
Level_1
- 538 -
[Off Delay Timer]
0 t
&
≥1
0.000-300.000s
1
&
On
Normal
[BI1-CPL]
Off
Inverse
0 t
&
≥1
0.000-300.000s
1
&
On
Normal
[BI2-CPL]
Off
Inverse
0 t
&
≥1
0.000-300.000s
1
&
On
Normal
[BI3-CPL]
Off
Inverse
0 t
&
≥1
0.000-300.000s
1
&
On
Normal
[BIn-CPL]
Off
Inverse
R
[BITH2]
R
R
6F2T0200 (0.15)
8001001172
To internal
BI1-CPL
&
≥1
&
8101011172
BI2-CPL
&
≥1
&
8201021172
BI3-CPL
&
≥1
&
8**********
BIn-CPL
&
≥1
&
BI
GRE200 (1,2)