Toshiba TLCS-900/H1 Series Manual page 110

BEXCSH Bit symbol
(0159H)
Read/Write
Reset State
BEXCSL Bit symbol
(0158H)
Read/Write
Reset State
PMEMCR Bit symbol
(0166H)
Read/Write
Reset State
BROMCR Bit symbol
(0167H)
Read/Write
Reset State
Note: Read-modify-write is prohibited for BEXCSH and BEXCSL registers.
(2) Operation after reset release
The start data bus width is determined by the state of AM1/AM0 pins just after reset
release. The external memory is then accessed as follows
Note: The memory to be used on starting after reset must be either NOR flash or masked ROM.
AM1/AM0 pins are valid only just after reset release. In other cases, the data bus
width is set by the control register <BnBUS1:0> .
On reset, only the control register (B2CSH/B2CSL) of the block address area 2
becomes effective automatically (B2CSH<B2E> is set to "1" on reset).
The data bus width which is specified by AM1/AM0 pins is loaded to the bit for
specification of the bus width of the control register in the block address area 2.
The block address area 2 is set to 000000H to FFFFFFH address on reset
(B2CSH<B2M> is reset to "0").
After reset release, the block address areas are specified by the memory start
address register (MSARn) and the memory address mask register (MAMRn). The
control register (BnCS) is then set.
Set the enable bit (BnE) of the control register to "1" to enable the setting.
Table 3.6.2 Control Register
7 6 5
BEXWW2 BEXWW1
W
0 1
AM1 AM0
0 0
0 1
1 0
1 1
NAND flash and SDRAM cannot be used.
92CH21-108
4 3
BEXOM1
0
BEXWW0
0
OPGE OPWR1
0 0
Start Mode
Don't use this setting
Start with 16-bit data bus (Note)
Start with 32-bit data bus (Note)
Start with boot (32-bit internal MROM)
TMP92CH21
2 1
BEXOM0 BEXBUS1 BEXBUS0
W
0 0
BEXWR2 BEXWR1 BEXWR0
W
0 1
OPWR0 PR1
R/W
0 1
ROMLESS VACE
R/W
0/1
2009-06-19
0
0
0
PR0
0
1/0