Toshiba TLCS-900/H1 Series Manual page 117
Original cmos 32-bit microcontroller
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(6) Basic bus timing
(a) External read/write cycle (0 waits)
SDCLK
(20 MHz)
CSn
A23 to A0
,
RD
SRxxB
D31 to D0
,
SRWR
WRxx
D31 to D0
(b) External read/write cycle (1 wait)
SDCLK
(20 MHz)
CSn
A23 to A0
,
RD
SRxxB
D31 to D0
,
SRWR
SRxxB
WRxx
D31 to D0
T1
SRxxB
Output
T1
TW
92CH21-115
T2
Read
Input
Write
T2
Input
Output
TMP92CH21
Read
Write
2009-06-19
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