Toshiba TLCS-900/H1 Series Manual page 367

Original cmos 32-bit microcontroller

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3.14.5.1 Gate Driver Control

The TFT gate driver is controlled bybase clock LCP1and vertical shift data signal

LBCD. This LSI has 3-bit output enable signals LGOE2 to LGOE0which can be

controlled individually. The TFT gate driver's output can be controlled by this timing

and is available for blanking adjustment and zoom function.

The LBCD signal begins output from rising of LCP1 and the TFT gate driver

recognizes the start point of the vertical direction. LGOE0 then outputs from rising of

LCP1 and repeats. LGOE1 outputs one LCP1 clock delayed. LGOE2 delay one LCP1

clock from LGOE1. By LCDCTL1<LBCDW1:0> setting, the width of LBCD can be

selected from 1, 2, or 3 clocks of LCP1.

1. The cycle of LBCD is determined by the setting of (LCDFFP) register.

2. Enable width of LBCD is selectable from (1×LCP1) to (3×LCP1).

LCP1 counter

*Pre LCP1_SET

Note 1: LCP1 counter (LCDFFP) : 1024 clocks maximum

Note 2: Pre_LCP1_SET (LCDCCR0) : 8 clocks (3bits) of LCP1 maximum

Figure 3.14.19 Example of TFT Gate Driver Timing Control

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