Toshiba TLCS-900/H1 Series Manual page 115

(4) Wait control
The external bus cycle completes a wait of at least two states (100 ns at f
MHz).
Setting the <BnWW2:0> and <BnWR2:0> of BnCSL specifies the number of waits in
the write cycle and the read cycle. <BnWW2:0> is set using the same method as
<BnWR2:0>.
<BnWW>/<BnWR> (BnCSL Register)
<BnWW2> <BnWW1>
<BnWR2> <BnWR1>
0
0
1
1
1
0
Note 1: For SDRAM, the above setting is ineffective. Refer to 3.16 SDRAM controller.
Note 2: For NAND flash, this setting is ineffective.
For RAM built-in LCDD, this setting is effective.
(i) Waits number fixed mode
The bus cycle is completed following the number of states set. The number of
states is selected from 2 states (0 waits) to 6 states (4 waits).
(ii) pin input mode
WAIT
This mode samples the
continuously while the signal is active. The bus cycle is a minimum 2 states. The
bus cycle is completed if the wait signal is non active ("High" level) at the second
state. The bus cycle continues if the wait signal is active after 2 states or more.
<BnWW0>
<BnWR0>
0 1 2 states (0 waits) access fixed mode
1 0 3 states (1 wait) access fixed mode (Default)
0 1 4 states (2 waits) access fixed mode
1 0 5 states (3 waits) access fixed mode
1 1 6 states (4 waits) access fixed mode
1 1
WAIT
Others (Reserved)
input pins. In this mode, a wait is inserted
WAIT
92CH21-113
Function
pin input mode
TMP92CH21
= 20
SYS
2009-06-19