Toshiba TLCS-900/H1 Series Manual page 364

3.14.4.5 Setting Each Control Signals
The TFT source driver is controlled by base clock (LCP0), data start clock (LFR) and
load pulse (LLP). Special data bus LD11 to LD0 uses 8 bits or 12 bits for suitable LCD
driver.
The timing of each signal can be finely adjusted using the relevant control register.
When using the TFT driver a large amount of data is required. So, when using wide
bus and high speed transmission, some noise may be generated. This LSI has an LDIV
function. This function automatically sets the minimum data change method, from
inverting data and LDIV signal, to comparing current data with the previous data. If
the TFT LCD driver supports the data inverting function, it is possible to decrease the
noise.
The following shows basic timings.
LFR
(Support to DVM setting)
LCP1
(Rise up)
LBCD
(Low Enable setting)
LLP
Horizontal Front Porch
(LCDCCR0)
(Counter LCP1: 3-bit)
This example shows register
value "0".
LLP (Mode1)
LLP (Mode2)
LCP0
(Rise up)
LD11 to LD0
1 2 3 4 5
Horizontal Front Porch (LCDCCR1)
: 8 clocks × 5-bit counter)
(f
SYS
This example shows register value "0"
Offset time is fsys(14 to 16
1 2 3 4 5 6 7 8 9
Figure 3.14.17 Timing Diagram of TFT Driver Control
92CH21-362
6 7 8 9 COM
SEG
High Width Control(LCDCCR2)
: 8 clocks × 8-bit counter)
(f
SYS
When register is set "0", high level
width is out when LD bus data is valid.
TMP92CH21
Gate driver
control
Vertical Back Porch
(No control counter)
Horizontal Back Porch
.
(No control counter)
Source
driver control
2009-06-19