Toshiba TLCS-900/H1 Series Manual page 351

(3) Divide frame adjust function
in large LCD panels.
alternates between high and low level with each LLP cycle for the LCDDVM
register values given below.
alternates between high and low level with each LBCD cycle. This function is not
affected by the LBCD timing.
Note: Availability of this function depends on the actual LCD driver or LCD panel used.
LCDDVM Bit symbol FMN7
(0283H)
Read/Write
Reset State
Function
(Reference) In general, prime numbers (3, 5, 7, 11, 13 ...) are best for the value of the LCDDVM
register.
The DIVIDE FRAME function allows for adjustments to reduce uneven display
When this function is enabled by setting <FRMON> = 1, the LFR signal
When this function is disabled by setting <FRMON> = 0, the LFR signal
We recommend checking that register's value when used in the proposed
environment.
Divide Frame Register
7 6 5
FMN6 FMN5
0 0 0
92CH21-349
4 3
FMN4 FMN3 FMN2
R/W
0 0
Setting DVM bit7 to bit0
TMP92CH21
2 1 0
FMN1 FMN0
0 0 0
2009-06-19