Toshiba TLCS-900/H1 Series Manual page 260

SETUP DATA0 ACK
INT_SETUP
INT_ ENDPOINT0
INT_STATUS
REQUEST FLAG
DATASET register
BRD
BWR
bmRequestType register
bRequest register
wValue register
wIndex register
wLength register
Figure 3.10.6 The Control Flow in UDC (Control Read Transfer Type)
Stage change condition of control read transfer type
1. Receive SETUP token from host
• Start setup stage in UDC.
•
Receive data in request normally and judge. And assert INT_SETUP
interrupt externally.
•
Change data stage in the UDC.
2. Receive IN token from host
• The CPU receives a request from the request register every
INT_SETUP interrupt.
• Judge request and access Setup Received register to inform the UDC
that INT_SETUP interrupt has been recognized .
• According to Device request, monitor EP0 bit of DATASET register,
and write data to FIFO.
•
If the UDC is set data of payload to FIFO or CPU set short packet
transfer in EOP register, EP0 bit of DATASET register is set.
•
The UDC transfers data that is set to FIFO to host by IN token
interrupts.
• When the CPU finishes transaction, it writes "0" to EP0 bit of EOP
register.
• Change status stage in the UDC.
3. Receive OUT token from host.
• Return ACK to OUT token and change state to IDLE in the UDC.
•
Assert INT_STATUS interrupt externally.
These changing conditions are shown in Figure 3.10.6.
IN NAK IN DATA1
Setup Received register
92CH21-258
ACK IN DATA0 ACK
EP0_FIFO (Rest data)
EP0_FIFO (WR of payload)
TMP92CH21
OUT DATA1 ACK
EOP register
2009-06-19