Toshiba TLCS-900/H1 Series Manual page 419

(4) Capture registers (TB0CP0H/L and TB0CP1H/L)
These 16-bit registers are used to latch the values in the up counters.
All 16 bits of data in the capture registers should be read. For example, using a
2-byte data load instruction or two 1-byte data load instructions. The least significant
byte is read first, followed by the most significant byte.
The addresses of the capture registers are as follows:
TMRB0
TB0CP0H/L
Upper 8 bits
(TB0CPH)
00118DH
The capture registers are read-only registers and thus cannot be written to.
(5) Capture input control
This circuit controls the timing to latch the value of the up counter UC10 into
TB0CP0H/L and TB0CP1H/L.
The value in the up counter can be loaded into a capture register by software.
Whenever 0 is programmed to TB0MOD<TB0CP0I>, the current value in the up
counter is loaded into capture register TB0CP0H/L. It is necessary to keep the
prescaler in run mode (i.e., TB0RUN<TB0PRUN> must be held at a value of 1).
(6) Comparators (CP10 and CP11)
CP10 and CP11 are 16-bit comparators which compare the value in the up counter
UC10 with the value set in TB0RG0H/L or TB0RG1H/L respectively, in order to detect
a match. If a match is detected, the comparator generates an interrupt (INTTB00 or
INTTB01 respectively).
(7) Timer flip-flops (TB0FF0)
These flip-flops are inverted by the match detect signals from the comparators and
the latch signals to the capture registers. Inversion can be enabled and disabled for
each element using TB0FFCR<TB0C1T1, TB0C0T1, TB0E1T1 and TB0E0T1>.
After a reset the value of TB0FF0 is undefined. If "00" is programmed to TB0FFCR
<TB0FF0C1:0>, TB0FF0 will be inverted. If "01" is programmed to the capture
registers, the value of TB0FF0 will be set to "1". If "10" is programmed to the capture
registers, the value of TB0FF0 will be cleared to "0".
The values of TB0FF0 can be output via the timer output pin TB0OUT0 (which is
shared with PC6). Timer output should be specified using the port B function register.
Lower 8 bits Upper 8 bits
(TB0CP0L) (TB0CP1H)
00118CH 00118FH
92CH21-417
TB0CP1H/L
Lower 8 bits
(TB0CP1L)
00118EH
TMP92CH21
2009-06-19