Toshiba TLCS-900/H1 Series Manual page 257

(c-2) Data stage
Data stage is configured by one or several transactions based on toggle
sequence.
The transaction is the same as for format transmission or receiving bulk
transaction except for the following differences:
• Toggle bit starts from "1" by SETUP stage.
• It determines whether right or not by comparing IN and OUT token with
direction bit of device request. If a token of the opposite direction is
received, it is recognized as status stage.
• INT_ENDPOINT0 interrupt is asserted.
(c-3) Status stage
Status stage is configured 0-data-length packet with DATA1's PID and
handshake IN or OUT token. It uses a transaction in the opposite direction to the
preceding stage.
The combination is given below.
• Control read transfer type: OUT
• Control write transfer type: IN
• Control write transfer type (not dataphase): IN
UDC processes status stage base of control flow in control transfer type. At this
point, CPU must write "0" to EP0 bit of EOP register in last transaction for status
stage to finish normally.
Details of status stage are given below.
(c-3-1) IN status stage
IN status stage transaction format is given below.
• Token: IN
• Data: DATA1 (0 data length), NAK, STALL
•
Handshake: ACK
Control flow
The transaction flow of IN status stage in UDC is given below.
1. Token packet is received and address, endpoint number and error are
confirmed. If it does not corrspond, the state returns to IDLE. If
status stage is enabled based on stage control flow in the UDC,
advance to next stage.
2. STATUS register state is confirmed.
• INVALID condition: State returns to IDLE.
•
STALL condition: Stall handshake is returned and state returns
Confirmation of whether EOP register is accessed or not is carried
out externally. If it is not accessing, NAK handshake is returned to
continue control transfer, and state returns to IDLE.
3. If EOP register access is confirmed, 0-data-length data packet and
CRC are transmitted.
to IDLE.
92CH21-255
TMP92CH21
2009-06-19