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Toshiba TLCS-900/H1 Series Manual page 229

Original cmos 32-bit microcontroller
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3.10.3.22 INT_Control Register
this register.
becomes disabled.
INT_Control
bit Symbol
(07D6H)
Read/Write
Reset State
(smaller than the data length that is specified by the host as wLength), the device side
and stage management cannot be synchronized. Therefore, INT_STATUSNAK
interrupt signals this shift to status stage. If needed, set to "1" after receiving setup
packet.
3.10.3.23 USB STATE Register
bit Symbol
USB STATE
(07CEH)
Read/Write
Reset State
Note: When writing to this register, a recovery time of 5clocks at 12MHz is needed. After writing this register, insert
dummy instruction of 420 ns or longer.
these bits (Configured, Addressed and Default). If transaction for SET_CONFIG
request is executed using software, write the present state to this register. If host
appointconfig is 0, this becomes Unconfigured, and it is necessary to return to
Addressed state. Therefore, if host appoint config is 0, write "0" to bit2.
by hardware. When host appoint config value that supported by device, the device
must execute mode setting for each endpoint by using the value that is appointed by
endpoint-descriptor in the config-descriptor. After finish mode setting, set Configured
bit (Bit2) to "1" before accessing EOP register. When this bit is set to "1", Addressed bit
(Bit1) is set to "0" automatically.
INT_STATUS_NAK interrupt is disabled and enabled by the value that is written to
This is initialized to disable by external reset. When setup packet is received, it
7
6
In control read transfer, if the host terminates a dataphase with small data length
STATUS_NAK (Bit0)
0: INT_STATUS_NAK interrupt disable
1: INT_STATUS_NAK interrupt enable
This register shows the current device state for connection with USB host.
7
6
Inside the UDC, the answer for each Device Request is managed by referring to
When Configured bit (Bit2) is written "0", Addressed bit (bit 1) is set automatically
Bit2 to bit0
000: Default
010: Addressed
100: Configured
5
4
5
4
92CH21-227
TMP92CH21
3
2
1
3
2
1
Configured
Addressed
R/W
R
0
0
0
Status_nak
R/W
0
0
Default
R
1
2009-06-19

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