Toshiba TLCS-900/H1 Series Manual page 374

Original cmos 32-bit microcontroller

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3.14.6.3 Sequential Access Type

Data transmission to the LCD driver is executed by a transmit instruction from the

After setting operation mode to the control register, when a CPU transmit

instruction is executed the LCDC outputs a chip select signal to the LCD driver

connected externally by the control pin (LCP0...). Therefore control of data

transmission numbers corresponding to LCD size is controlled by CPU instruction.

There are 2 kinds of LCD driver address in this case, which are selected by the

LCDCTL<MMULCD> register.

This corresponds to a LCD driver which has each 1 byte of instruction register and

display data register in LCD driver when <MMULCD> = "0". Please select the

transmission address at this time from 1FE0H to 1FE7H.

LCDC0L/LCDC0H/LCDC1L/LCDC1H/LCDC2L/LCDC2H/LCDR0L/LCDR0H Register

System clock: f

Note 1: This waveform is in the case of 3-state access.

Note 2: Rising timing of chip enable signal (e.g LCP0) is different.

Figure 3.14.22 Example of Access Timing for Built-in RAM Type LCD Driver (Wait = 0)

Depends on external LCDD specification

[Write cycle]

WAIT sampling

[Read cycle]

Tmp92ch21fg Jtmp92ch21