Toshiba TLCS-900/H1 Series Manual page 361

3.14.4 TFT Color Display Mode
3.14.4.1 Description of Operation
This is basically the same setting as for SR mode.
Set the mode of operation, start address of source data save memory, color level and
LCD size to control registers before setting start register.
After setting start register, the LCDC outputs a bus release request to the CPU and
reads data from source memory. After data reading from source data is completed, the
LCDC cancels the bus release request and the CPU will restart. The LCDC then
transmits LCD size data to the external LCD driver through the LD bus (the special
data bus only for LCD driver). At this time, the control signals (LCP0 etc.) connected
to the LCD driver output the specified waveform which is synchronized with the data
transmission.
In TFT mode LCDC, the CPU is stopped by the internal BUSREQ signal during
data read from source memory (during DMA operation).
The LCD controller generates control signals (LFR, LBCD, LLP etc.) from base clock
LCDSCC. LCDSCC is the base clock for the LCD controller, which is generated by
system clock f
For TFT source driver, the following signals are supported: 8-bit RGB or 4-bit × RGB
special data bus and LCP0, LFR, LLP and LDIV.
And for TFT gate driver control, LCP1, LBCD and LGOE2 to LGOE0.
3.14.4.2 Memory Space
Memory space setting is the same as for SR mode. Refer to SR mode section.
3.14.4.3 Mapping of Display Memory and Panning Function
Panning function and display memory mapping are the same as for SR mode. Refer
to SR mode section.
3.14.4.4 Data Transmission
This LSI outputs display data form special bus for LCD driver. The LCD driver
input width can be selected. 8-bit and 12-bit widths are supported.
SYS
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92CH21-359
TMP92CH21
2009-06-19