Toshiba TLCS-900/H1 Series Manual page 124

3.6.6 Cautions
(1) Note on timing between
If the parasitic capacitance of the
(Chip select signal), it is possible that an unintended read cycle occurs due to a delay in
the read signal. Such an unintended read cycle may cause a problem, as in the case of
(a) in Figure 3.6.3.
SDCLK
(20 MHz)
A23 to A0
CSm
CSn
RD
Example: When using an externally connected NOR flash which uses JEDEC standard
When the toggle bit is reversed by this unexpected read cycle, the CPU cannot read
the toggle bit correctly since it always reads same value for the toggle bit. To avoid this
phenomenon, data polling function control is recommended.
and
RD
CS
Figure 3.6.3 Read Signal Delay Read Cycle
commands, note that the toggle bit may not be read out correctly. If the read
signal in the cycle immediately preceding the access to the NOR flash does not
go high in time, as shown in Figure 3.6.4, an unintended read cycle like the one
shown in (b) may occur.
Memory access
SDCLK
(20 MHz)
A23 to A0
NOR flash
chip select
RD
Toggle bit
Figure 3.6.4 NOR Flash Toggle Bit Read Cycle
92CH21-122
(Read signal) is greater than that of the
RD
(a)
Toggle bit RD cycle
(b)
TMP92CH21
CS
2009-06-19