Toshiba TLCS-900/H1 Series Manual page 15

3.1.2 Reset Operation
When resetting the TMP92CH21, ensure that the power supply voltage is within the
operating voltage range, and that the internal high-frequency oscillator has stabilized.
Then hold the
At reset, since the clock doubler (PLL) is bypassed and the clock-gear is set to 1/16, the
system clock operates at 1.25 MHz (fc = 40 MHz).
When the reset has been accepted, the CPU performs the following:
•
Sets the program counter (PC) as follows in accordance with the reset vector stored
at address FFFF00H to FFFF02H:
PC<7:0>
PC<15:8>
PC<23:16>
• Sets the stack pointer (XSP) to 00000000H.
• Sets bits <IFF2:0> of the status register (SR) to 111 (thereby setting the interrupt
level mask register to level 7).
•
Clears bits <RFP1:0> of the status register to 00 (there by selecting register bank
0).
When the reset is released, the CPU starts executing instructions according to the
program counter settings. CPU internal registers not mentioned above do not change when
the reset is released.
When the reset is accepted, the CPU sets internal I/O, ports and other pins as follows.
• Initializes the internal I/O registers as shown in the "Special Function Register"
table in section 5.
•
Sets the port pins, including the pins that also act as internal I/O, to
general-purpose input or output port mode.
Internal reset is released as soon as external reset is released.
Memory controller operation cannot be ensured until the power supply becomes stable
after power-on reset. External RAM data provided before turning on the TMP92CH21 may
be corrupted because the control signals are unstable until the power supply becomes
stable after power on reset.
VCC (3.3 V)
RESET
High-frequency oscillation stabilized time
input low for at least 20 system clocks (16 µs at fc = 40 MHz).
RESET
← data in location FFFF00H
← data in location FFFF01H
← data in location FFFF02H
+20 system clock
Figure 3.1.1 Power on Reset Timing Example
92CH21-13
TMP92CH21
0 s (Min)
2009-06-19