TMP92CH21
2.
Disabling the clock
A clock carry over is prohibited when "0" is written to PAGER<ENATMR> in
order to prevent malfunction caused by the Carry hold circuit. While the clock is
prohibited, the Carry hold circuit holds a one sec. carry signal from a divider.
When the clock becomes enabled, the carry signal is output to the clock, the time
is revised and operation continues. However, the clock is delayed when
clock-disabled state continues for one second or more. Note that at this time
system power is down while the clock is disabled. In this case the clock is stopped
and clock is delayed.
Start
Disable the clock
Read the clock data
Enable the clock
End
Figure 3.13.4 Flowchart of Clock disable
2009-06-19
92CH21-329