Toshiba TLCS-900/H1 Series Manual page 147

System clock Clock gear
−
SYSCR0 SYSCR1
<SYSCK> <GEAR2:0>
−
1(fs)
000(x1)
001(x2)
×8
0(fc)
010(x4)
011(x8)
100(x16)
(5) Settings for each mode
Table 3.7.5 shows the SFR settings for each mode.
Register name
<Bit Symbol>
Function
8-bit timer × 2 channels
16-bit timer mode
8-bit PPG × 1 channel
8-bit PWM × 1 channel
8-bit timer × 1 channel
−: Don't care
Table 3.7.4 PWM Cycle
6
2 (x64)
TAxxMOD<TAxCLK1:0>
φT1(x2) φT4(x8) φT16(x32)
1024/fs 4096/fs 16384/fs
1024/fc 4096/fc 16384/fc
2048/fc 8192/fc 32768/fc
4096/fc 16384/fc 65536/fc
8192/fc 32768/fc 131072/fc
16384/fc 65536/fc 262144/fc
Table 3.7.5 Timer Mode Setting Registers
<TA01M1: 0> <PWM01: 00>
Timer Mode PWM Cycle
−
00
−
01
−
10
6
2 , 2
11
(01, 10, 11)
−
11
92CH21-145
PWM cycle
TAxxMOD<PWMx1:0>
7
2 (x128)
TAxxMOD<TAxCLK1:0>
φT1(x2) φT4(x8) φT16(x32)
2048/fs 8192/fs
2048/fc 8192/fc
4096/fc 16384/fc
8192/fc 32768/fc
16384/fc 65536/fc
32768/fc 131072/fc
TA01MOD
<TA1CLK1: 0>
Upper Timer
Input Clock
Lower timer
match,
φT1, φT16, φT256
(00, 01, 10, 11)
−
−
7 8
, 2
−
φT1, φT16, φT256
(01, 10, 11)
TMP92CH21
8
2 (x256)
TAxxMOD<TAxCLK1:0>
φT1(x2) φT4(x8)
32768/fs 4096/fs 16384/fs
32768/fc 4096/fc 16384/fc
65536/fc 8192/fc 32768/fc
131072/fc 16384/fc 65536/fc
262144/fc 32768/fc 131072/fc
524288/fc 65536/fc 262144/fc
TA1FFCR
<TA0CLK1: 0> <TA1FFIS>
Timer F/F
Lower Timer
Input Clock
Invert Signal Select
External clock,
0: Lower timer output
φT1, φT4, φT16
1: Upper timer output
(00, 01, 10, 11)
External clock,
φT1, φT4, φT16
(00, 01, 10, 11)
External clock,
φT1, φT4, φT16
(00, 01, 10, 11)
External clock,
φT1, φT4, φT16
(00, 01, 10, 11)
−
Output disabled
φT16(x32)
65536/fs
65536/fc
131072/fc
262144/fc
524288/fc
1048576/fc
−
−
−
2009-06-19