Toshiba TLCS-900/H1 Series Manual page 39

Original cmos 32-bit microcontroller

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(3) Operation

In IDLE2 mode only specific internal I/O operations, as designated by the

IDLE2 setting register, can take place. Instruction execution by the CPU stops.

Figure 3.3.7 illustrates an example of the timing for clearance of the IDLE2

mode halt state by an interrupt.

Interrupt for

Figure 3.3.7 Timing Chart for IDLE2 Mode Halt State Cleared by Interrupt

In IDLE1 mode, only the internal oscillator and the RTC and MLD continue to

operate. The system clock stops.

In the halt state, the interrupt request is sampled asynchronously with the

system clock; however, clearance of the halt state (e.g., restart of operation) is

synchronous with it.

Figure 3.3.8 illustrates the timing for clearance of the IDLE1 mode halt state by

an interrupt.

Interrupt for

Figure 3.3.8 Timing Chart for IDLE1 Mode Halt State Cleared by Interrupt

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