Toshiba TLCS-900/H1 Series Manual page 337

LCDCCR0 Bit symbol
(0288H)
Read/Write
Reset State
Function
LCDCCR1 Bit symbol
(0289H)
Read/Write
Reset State
Function
LCDCCR2 Bit symbol LLPSU7
(028AH)
Read/Write
Reset State
Function
LCD Clock Counter Register 0
7 6 5
LCD Clock Counter Register 1
7 6 5
LCD Clock Counter Register 2
7 6 5
LLPSU6 LLPSU5
R/W R/W R/W
0 0 0
TFT source driver, LLP_Enable signal: f
92CH21-335
4 3
4 3
TLDE4 TLDE3
R/W R/W
0 0
LLP_Set-up time: f
Set up time for TFT source driver LLP signal
(Offset of f
4 3
LLPSU4 LLPSU3
R/W R/W
0 0
High width time for LLP signal
TMP92CH21
2 1
PCPV2 PCPV1
R/W R/W
0 0
Pre LCP1 CLK: LCP1 pulse number
Dummy clock number until valid clock
of gate driver LCP1
2 1
TLDE2 TLDE1
R/W R/W
0 0
pulse × 8
SYS
14∼16 pulse)
SYS
2 1
LLPSU2 LLPSU1 LLPSU0
R/W R/W
0 0
× 8
SYS
2009-06-19
0
PCPV0
R/W
0
0
TLDE0
R/W
0
0
R/W
0