Toshiba TLCS-900/H1 Series Manual page 99

PF Bit symbol
(003CH)
Read/Write
Reset State
PFCR Bit symbol
(003EH)
Read/Write
Reset State
Function
PFFC Bit symbol PF7F
(003FH)
Read/Write
Reset State
Function 0: Output
1: SDCLK
PF2 Setting
<PF2C>
0
<PF2F>
Input port or
SCLK1, input or
CTS 1
0
SCLK0, input
CTS 0
From PF2 pin at <PF2> = 0
From P92 pin at <PF2> = 1
1 SCLK1 output
PFFC2 Bit symbol
(003DH)
Read/Write
Reset State
Function
PFDR Bit symbol PF7D
(008FH)
Read/Write R/W
Reset State
Function Input/Output
buffer drive
register for
standby
mode
Note: Read-modify-write is prohibited for the registers PFCR, PFFC and PFFC2.
Port F Register
7 6 5
PF7
R/W
1
Port F Control Register
7 6 5
Port F Functon Register
7 6 5
W
1
PF1 Setting
<PF1C>
1
<PF1F>
0
RXD0/RXD1 input
1
Output
port
SCLK0
output
Port F Functon Register 2
7 6 5
Port F Drive Register
7 6 5
1
Figure 3.5.35 Register for Port F
92CH21-97
4 3
4 3
4 3
0 1
Input port or Output
port
4 3
4 3
TMP92CH21
2 1
PF2 PF1
R/W
External data
(Output latch register is set to "1")
2 1
PF2C PF1C
W
0 0
Refer to following table
2 1
PF2F PF1F
W
0 0
Refer to RXD0 pin
following
selection
table
0: Port F1
1: Port 91
PF0 Setting
<PF0C>
0
<PF0F>
0 Input port Output port
1 TXD1 output TXD0 output
2 1
2 1
PF2D PF1D
R/W
1 1
Input/Output buffer drive register for
standby mode
2009-06-19
0
PF0
0
PF0C
0
0
PF0F
0
Refer to
following
table
1
0
PF0F2
W
0
Output buffer
0: CMOS
1: Open drain
0
PF0D
1