Toshiba TLCS-900/H1 Series Manual page 417

Original cmos 32-bit microcontroller

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Operation of Each Block

(1) Prescaler

The 5-bit prescaler generates the source clock for timer 0. The prescaler clock (φT0) is

a divided clock (divided by 8) from the f

This prescaler can be started or stopped using TB0RUN<TB0PRUN>. Counting

starts when <TB0PRUN> is set to 1; the prescaler is cleared to 0 and stops operation

when <TB0PRUN> is cleared to 0.

System clock

(2) Up counter (UC10)

UC10 is a 16-bit binary counter which counts up pulses input from the clock specified

by TB0MOD<TB0CLK1:0>.

Any one of the prescaler internal clocks φT1, φT4 and φT16 can be selected as the

input clock. Counting or stopping and clearing of the counter is controlled by

TB0RUN<TB0RUN>.

When clearing is enabled, the up counter UC10 will be cleared to 0 each time its

value matches the value in the timer register TB0RG1H/L. If clearing is disabled, the

counter operates as a free-running counter.

Clearing can be enabled or disabled using TB0MOD<TB0CLE>.

A timer overflow interrupt (INTTBOF0) is generated when UC10 overflow occurs.

Table 3.18.2 Prescaler Clock Resolution

Timer counter input clock

TMRB prescaler

TB0MOD<TB0CLK1:0>

Tmp92ch21fg Jtmp92ch21