Toshiba TLCS-900/H1 Series Manual page 383

3.16 SDRAM Controller (SDRAMC)
The TMP92CH21 includes an SDRAM controller which supports SDRAM access by
CPU/LCDC.
The features are as follows.
(1) Support SDRAM
Data rate type:
Bulk of memory:
Number of banks:
Width of data bus:
Read burst length:
Write mode:
(2) Initialize function
All banks precharge command
8 times auto refresh command
Set the mode register command
(3) Access mode
Read burst length
Addressing mode
CAS latency (clock)
Write mode
(4) Access cycle
CPU Access (Read/write)
Read cycle:
Write cycle:
Access data width:
LCDC Burst Access (Read only)
Read cycle:
Over head:
Access data width:
(5) Refresh cycle auto generate
Auto-refresh is generated while another area is being accessed.
Refresh interval is programmable.
Self-refresh is supported
Note 1: Display data for LCDC must be set from the head of each page.
Note 2: Condition of SDRAM's area set by CS1 or CS2 setting of memory controller.
Only SDR (Single data rate) type
16/64/128/256/512 Mbits
2/4 banks
16/32
1 word/full page
Single/burst
CPU Access
1 word/full page selectable
Sequential
2
Single/burst selectable
1 word− 4 states/full page − 1 state
Single − 3 states/burst − 1 state
8 bits/16 bits/32 bits
= 20 MHz)
1 word (50 ns at f
SYS
4 states (200 ns at f
SYS
16 bits/32 bits
92CH21-381
LCDC Access
Full page
Sequential
2
−
= 20 MHz)
TMP92CH21
2009-06-19