Toshiba TLCS-900/H1 Series Manual page 355

Internal system clock
(f )
SYS
A23 to A0
RD
D32 to D0 or D15 to D0
8-bit bus
LCP0 (2CP)
LD7 to LD0
LCP0 (4CP)
LD7 to LD0
LCP0 (8CP)
LD7 to LD0
4-bit bus
LCP0 (2CP)
LD3 to LD0
LCP0 (4CP)
LD3 to LD0
Figure 3.14.10 Fastest Timing Diagram for External SRAM, 0 waits
4-/8-bit bus
LCP0 (2CP)
LD7 to LD0
∗ When using internal SRAM, always select 32-bit bus width and 0 waits, 1 clocks access.
N N + 1 N + 2
IN IN + 1 IN + 2
OUT + 1 OUT + 1 OUT + 2 OUT + 2 OUT + 3 OUT + 3 OUT + 4 OUT + 4
OUT OUT
OUT
OUT + 1 OUT + 1 OUT + 2 OUT + 2 OUT + 3 OUT + 3 OUT + 4 OUT + 4
OUT OUT
OUT
OUT + 1 OUT + 1 OUT + 2 OUT + 2 OUT + 3 OUT + 3 OUT + 4 OUT + 4
OUT OUT
Figure 3.14.11 Timing Diagram for Internal SRAM
92CH21-353
N + 3 N + 4 N + 5
IN + 3 IN + 4 IN + 5
OUT + 1 OUT + 2 OUT + 3
OUT
OUT + 1 OUT + 2 OUT + 3
TMP92CH21
32-bit bus width, monochrome
/4 grayscales/256 colors
16-bit bus width, monochrome
/4 grayscales/256 colors
16-bit bus, 16 grayscales
32-bit bus, monochrome
/4/16 grayscales/256 colors
16-bit bus, monochrome
4/16 grayscales/256 colors
Monochrome/4/16 grayscales
/256 colors
2009-06-19