Toshiba TLCS-900/H1 Series Manual page 112

(iii) Example of register setting
To set the block address area 64 Kbytes from address 110000H, set the register
as follows.
Bit 7
Bit symbol M1S23
Specified value 0
M1S23 to M1S16 bits of the memory start address register MSAR1 correspond
with address A23 to A16.
A15 to A0 are set to "0". Therefore, if MSAR1 is set to the above mentioned
value, the start address of the block address area is set to address 110000H.
Bit 7
Bit symbol M1V21
Specified value 0
M1V21 to M1V16 and M1V8 bits of the memory address mask register MAMR1
are set whether addresses A21 to A16 and A8 are compared or not. In register
setting, "0" is "compare", and "1" is "do not compare". M1V15 to M1V9 bits
determine whether addresses A15 to A9 are compared or not with bit 1. A23 and
A22 are always compared.
When set as above, A23 to A9 are compared with the value that is set as the
start addresses. Therefore, 512 bytes (addresses 110000H to 1101FFH) are set as
block address area 1, and if it is compared with the addresses on the bus, the chip
select signal CS1 is set to "low".
The other block address area sizes are specified in the same way.
A23 and A22 are always compared with block address area 0. Whether A20 to
A8 are compared or not is determined by the register.
Similarly, A23 is always compared with block address areas 2 to 5. Whether A22
to A15 are compared or not is determined by the register.
Note 1: When the set block address area overlaps with the built-in memory area, or
Note 2: If an address area other than
MSAR1 Register
6 5
M1S22 M1S21 M1S20
0 0
MAMR1 Register
6 5
M1V20 M1V19 M1V18
0 0
both two address areas overlap, the block address area is processed
according to priority as follows.
Built-in I/O > Built-in memory > Block address area 0 > 1 > 2 > 3
as . Therefore, wait number and data bus width controls follow the
CSEX
setting of (BEXCSH, BEXCSL register).
CSEX
92CH21-110
4 3 2
M1S19 M1S18
1 0 0
4 3 2
M1V17 M1V16
0 0 0
to is accessed, this area is regarded
CS 0 CS 3
TMP92CH21
1 0
M1S17 M1S16
0 1
1 0
M1V8
M1V15 to M1V9
0 1
2009-06-19